Component die packages, such as those used in packaging semiconductor devices, have become larger and more complicated than those previously used. This has led to outgoing package warpage after the package assembly process. Package warp may create many problems for downstream users. For example, pin grid array (PGA) packages, warpage contributed to poor pin tip true position that may lead to pin rework. For land grid array (LGA) packages, the warpage may lead to high resistance or open contacts between the package and the socket. For ball grid array (BGA) packages, excessive warpage may lead to surface mount problems. In addition, BGA packages have JEDEC (Joint Electron Device Engineering Council) standards for warpage. With the larger and more complicated packages, these standards may be difficult to achieve.
In addition, current 90 nanometer (nm) wafer technologies may use low-k dielectric layers, such as porous cured dielectrics, in their build up layers. This requires that the package impose almost no stress on the die, as die stress can lead to cracks and bumps. These defects create multiple reliability issues for packages, including open failures, short failures, reliability stress failures and may result in component dysfunction failures.
In most cases, the package warpage is caused by the underfill epoxy cure process, generally performed at high temperatures. Current approaches may add a mechanical reinforcement to the package, increasing costs, or accepting the additional warpage, leading to wasted packages that do not meet the relevant standards. It is also possible to lower the cure temperature, but that largely depends upon the material properties and may compromise the quality and reliability of the components.